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VLSI Training Ahmedabad

VLSI or Very Large Scale Integration is a way through which integrated circuit is created by integrating millions of transistors into a single chip. This design has become the most happening field of electronics and is finding its application in diverse range of electrical equipment like computer peripherals, cell phones, satellites, defense aerospace, consumer electronics, set top entertainment boxes and several other devices. All those candidates, who are looking to build a career in VLSI field, Vector Institute offers training program in VLSI technologies, which is designed to meet the contemporary demands of the industry. Our VLSI technologies course trained candidates with various domains of chip design.

Our VLSI Design Course imparts ASIC, FPGA design flows, and trains engineers extensively on the VLSI design methodologies, CMOS, VHDL, Verilog and System Verilog. An unprecedented demand for the expert professionals of VLSI Design is encouraging us to offer course that geared towards meeting the increasing demand of the electronic industry.

Objectives of VLSI

  •   Provide an overview of the fundamental principles of VLSI, ASIC / FPGA design.
  •   Give the understanding of the characteristics of CMOS circuit construction.
  •   Impart experience designing integrated circuits using CAD tools.
  •   Analyse the basic building blocks of large-scale digital integrated circuits.
  •   Help design functional units such as adders, multipliers, ROMs, and SRAMs.

Advance VLSI Design and Verification Course

Module I

Introduction to VLSI

  •    What is VLSI? (introduction)
  •    VLSI / ASIC / SoC Flow
  •    FPGA, ASIC and SoC Concept, Introduction and detailed study
  •    EDA Tools Hands on and support
  •    Scope and Opportunities in Semiconductor Industry

Module II

Digital Electronics

  •    BCD, Excess-3, Gray Code conversion
  •    Digital number system
  •    Weighted and non-weighted binary numbers
  •    Logic Gates, Logic Minimization
  •    Any number system – Multiplication, Addition, Subtraction, Division
  •    Combinational Circuit, Sequential Circuit
  •    Finite State Machine
  •    Memories
  •    Excitation table concept
  •    Flip-flop Conversion
  •    Counter Structures and types
  •    Setup and Hold Violation, Hazards calculations

Module III

Verilog HDL

  •    Introduction
  •    Application and Abstraction levels of Verilog HDL
  •    Verilog Code Understanding
  •    Data types, Operators and Assignment types
  •    Constructs with application use
  •    Delays with usage
  •    Reset types with usage
  •    Task and Function with Applications
  •    System Task and Compiler Directives
  •    Self-checking TB and Code Coverage with Application
  •    Event scheduler
  •    STA Basics, Skew, Jitter, Metastability Concepts
  •    And all advance topics with real-time application usages
  •    Interview Question preparations

Module IV

System Verilog HVL

  •    Introduction with HDL limitations
  •    Verilog Vs. System Verilog
  •    System Verilog Evolution and Application
  •    Data Types
  •    Arrays with Enhancements and Applications
  •    Task and Function with Enhancements and Applications
  •    Interface
  •    Basic and Advance OOPs (Object Oriented Programming)
  •    Randomization
  •    Inter Process Communication
  •    Mailbox, Semaphore, Events
  •    System Verilog Event Scheduler
  •    And all special topics with real-time application usages
  •    Coverage Types with Applications
  •    Assertions With Applications

Module V

In-Depth Verification Process Cycle knowledge

  •    Types of Verification
  •    The Verification Plan
  •    Test-bench Components
  •    Multiple test cases and Regression

Module VI

UVM Methodology

  •    Introduction with HVL limitations
  •    Verilog Vs. System Verilog Vs. UVM
  •    UVM – Concept and Use
  •    UVM Factory
  •    UVM Phases and Reporting mechanism
  •    UVM Built-in Methods
  •    TLM Communication
  •    UVM Sequence
  •    Virtual Sequence Concept Real time Usage
  •    Virtual Sequencer and Sequence Arbitation
  •    Config DB
  •    UVM Callback
  •    UVM Environment Things

Module VII

Register Abstraction Layer (RAL)

  •    RAL – Flow, Model
  •    Register Adapter with methods
  •    Predictor with types of prediction
  •    Integration
  •    Register Layers
  •    Front door and Backdoor access

Module VII

Automation Zone

  •    Vim, Gvim automation
  •    Linux Support
  •    Industrial System Support
  •    SVN repository Hands-On
  •    And much more......

Module IX

Mini Projects

  1. 1. Verilog HDL :-
    •    Verilog Mini Projects Like (ALU, Timer, Watch dog timer, All types of Counters, shift registers) to learn RTL Design Concepts.
    •    Verilog Major Code Practice on RAM, ROM, FIFO, FSM and Arbiter with All types.
  2. 2. System Verilog HVL :-
    •    System Verilog Major Code Practice on RAM, ROM, FIFO to learn Design Verification Concepts.
  3. 3. UVM Methodology :-
    •    UVM Environment Creation on RAM, ROM, FIFO to learn Design Verification Concepts.

Module X

Major Industrial Project Hands-On With Expert Support

  •    Client Specification
  •    Design Architecture Creation
  •    RTL Design using Verilog HDL
  •    Design Verification using SV /UVM
  •    All Trending Protocols Support
  •    And much more......

Module XI

Interview Question-Answers

  •    Interview questions on Digital Electronics
  •    Interview questions on Verilog HDL
  •    Interview questions on System Verilog HVL
  •    Interview questions on UVM Methodology
  •    Weekly tests, Interview experience and much more….

We Provide Guidelines to develop reusable, efficient and generic Verification Environment with all Debugging Tips and Tricks.